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| d a t a sh eet preliminary speci?cation 2003 mar 13 integrated circuits SAA7715AH digital signal processor
2003 mar 13 2 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH contents 1 features 1.1 hardware 1.2 possible firmware 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 pll clock division factors for different clock inputs 8.2 the word select pll 8.3 the filter stream dac (fsdac) 8.3.1 interpolation filter 8.3.2 noise shaper 8.3.3 function of pin pom 8.3.4 power off plop suppression 8.3.5 pin vrefda for internal reference 8.3.6 supply of the analog outputs 8.4 external control pins 8.5 digital serial inputs/outputs and spdif inputs 8.5.1 digital serial inputs/outputs 8.5.2 spdif inputs 8.6 i 2 c-bus interface (pins scl and sda) 8.7 reset 8.8 power-down mode 8.9 power supply connection and emc 8.10 test mode connections (pins tscan, rtcb and shtcb) 9i 2 c-bus protocol 9.1 addressing 9.2 slave address (pin a0) 9.3 write cycles 9.4 read cycles 9.5 program ram 9.6 data word alignment 9.7 i 2 c-bus memory map specification 9.8 i 2 c-bus memory map definition 9.9 table definitions 10 software in rom description 11 limiting values 12 thermal characteristics 13 characteristics 14 i 2 s-bus timing 15 i 2 c-bus timing 16 application diagram 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 data sheet status 20 definitions 21 disclaimers 22 purchase of philips i 2 c components 2003 mar 13 3 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 1 features 1.1 hardware 24-bit philips 70 mips dsp core (24-bit data path and 12/24-bit coefficient path) 1.5 kbyte of downloadable dsp program memory (pram) 2 kbyte of dsp program memory (prom) 2.875 kbyte of re-programmable dsp data memory (xram) 1.5 kbyte of re-programmable dsp coefficient memory (yram) four stereo digital serial inputs (8 channels) with common bck and ws. to these inputs the i 2 s-bus format or lsb-justified formats can be applied one stereo bitstream dac (2 channels) with 64 fold oversampling and noise shaping selectable clock output (pin sysclk) for external slave devices (128f s to 512f s ) four stereo digital serial outputs (8 channels) with selectable i 2 s-bus or lsb-justified format two spdif inputs combined with digital serial input on-board ws_pll generates clock for on-board dac and output pin sysclk i 2 c-bus controlled (including fast mode) programmable phase-locked loop (pll) derives the clock for the dsp from the clk_in input - 40 to +85 c operating temperature range supply voltage only 3.3 v all digital inputs are tolerant for 5 v input levels power-down mode for low current consumption in standby mode optimized pinning for applications with other philips dacs (such as uda1334, uda1355 and uda1328). 1.2 possible ?rmware dolby? (1) pro logic decoding smoothed volume control (without zipper noise) automatic volume levelling (avl) dynamic bass enhancement ultra bass incredible surround incredible mono (imono) dpl virtualizer dolby digital virtualizer (dvd post-processing) dynamic compressor spectral enhancer equalizer with peaking/shelving filters dc filters bass/treble control dynamic loudness tone/noise generator graphical spectrum analyser configurable delay unit (dlu) sound steering/elevation for car applications sample rate conversion (src). 2 applications as co-processor for a car radio dsp in a car radio application for additional acoustic enhancements (sound steering/sound elevation/signal processing) multichannel audio: in dvd and home theatre applications as post-processing device such as signal virtualization (virtual 3d surround) and acoustic enhancement, tone control, volume control and equalizers multichannel decoding: dolby pro logic and virtual 3d surround pc/usb audio applications: stereo widening (incredible surround), sound steering, sound positioning and speaker equalization. (1) dolby available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation. 2003 mar 13 4 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 3 general description the SAA7715AH is a cost effective and powerful high performance 24-bit programmable dsp for a variety of digital audio applications. this dsp device integrates a 24-bit dsp core with programmable memories (program ram/rom, data and coefficient ram), 4 digital serial inputs, 4 digital serial outputs, 2 separate spdif receivers, a stereo fsdac, a standard philips i 2 c-bus interface, a phase-locked loop for the dsp clock generation and a second phase-locked loop for system clock generation (internal and external dac clocks). the SAA7715AH can be configured for various audio applications by downloading the dedicated dsp program code into the dsp program ram or using the rom or a combination of both. during the power-down mode the contents of the memories and all other settings will keep their values. the SAA7715AH can be initialized using the i 2 c-bus interface. several system application examples, based on this existing SAA7715AH, are available for a wide range of audio applications (e.g car radio dsp, dvd post-processing, dolby pro logic, pc/usb audio and more) which can be used as a reference design for customers. 4 quick reference data 5 ordering information symbol parameter conditions min. typ. max. unit v dd operating supply voltage all pins v dd with respect to pins v ss 3.15 3.3 3.45 v i ddd supply current of the digital part high activity of the dsp at dspfreq frequency - 95 - ma i dda supply current of the analog part zero input and output signal - 20 - ma p tot total power dissipation high activity of the dsp at dspfreq frequency - 380 - mw i powerdown dc supply current of the total chip in power-down mode pin powerdown enabled - 400 -m a f s sample frequency at iis_ws1, spdif1 or spdif2 input 32 44.1 96 khz (thd + n)/s dac total harmonic distortion-plus-noise to signal ratio of dac at 0 db -- 85 - db(a) at - 60 db -- 37 - db(a) s/n dac signal-to-noise ratio of dac code = 0 - 100 - db(a) f clk_in clock input frequency div_clk_in = low 8.192 11.2896 12.288 mhz div_clk_in = high 16.384 - 24.576 mhz dspfreq maximum dsp clock frequency -- 70 mhz type number package name description version SAA7715AH qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 2003 mar 13 5 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6 block diagram handbook, full pagewidth mhc320 SAA7715AH tcb pram prom dsp core stereo dac n f s clock i 2 c-bus ws_pll 2 pll 1 iis_bck1 2 24 25 4 iis_ws1 3 iis_in1 5 iis_in4 iis_out1 31 iis_out2 30 iis_out3 29 iis_out4 28 voutl 34 voutr 36 iis_bck 33 iis_ws 32 pom 39 vrefda 38 9 22 41 iis_in3 clk_in div_clk_in 6 dsp clock iis_in2 s xram yram 44 dsp_inout7 43 dsp_inout6 42 dsp_inout5 20 shtcb 19 rtcb v ssi2 26 tscan 27 10 v ssi1 14 v sse 21 v ssa2 15 v ddi1 16 v dde 23 v dda2 17 v dda1 spdif2 spdif1 reserved1 35 v ssa1 37 sysclk 18 dsp_reset 13 sda 12 scl 11 a0 40 powerdown 7 reserved2 8 reserved3 fig.1 block diagram. 2003 mar 13 6 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 7 pinning symbol pin pin type description iis_bck1 1 ipthdt5v bit clock signal belonging to data of digital serial inputs 1 to 4 iis_ws1 2 ipthdt5v word select signal belonging to data of digital serial inputs 1 to 4 iis_in1 3 ipthdt5v data pin of digital serial input 1 reserved1 4 ipthdt5v not to be connected externally iis_in4 5 ipthdt5v data pin of digital serial input 4 iis_in2 6 ipthdt5v data pin of digital serial input 2 reserved2 7 ipthdt5v not to be connected externally reserved3 8 ipthdt5v not to be connected externally iis_in3 9 ipthdt5v data pin of digital serial input 3 v ssi2 10 vssi ground supply (core only) (bond out to 2 pads) a0 11 ipthdt5v slave sub-address i 2 c-bus selection/serial data input test control block scl 12 iptht5v clock input of i 2 c-bus sda 13 iic400kt5v data input/output of i 2 c-bus v ssi1 14 vssis ground supply (core only) v ssa2 15 vssco ground supply analog of pll, ws_pll, spdif input stage v ddi1 16 vddi positive supply (core only) (bond out to 2 pads) v dda2 17 vddco positive supply analog of pll, ws_pll, spdif input stage dsp_reset 18 ipthut5v general reset of chip (active low) rtcb 19 ipthdt5v asynchronous reset test control block, connect to ground (internal pull down) shtcb 20 ipthdt5v shift clock test control block (internal pull down) v sse 21 vsse ground supply (peripheral cells only) clk_in 22 iptht5v system clock input v dde 23 vdde positive supply (peripheral cells only) spdif2 24 apio spdif2 data input (internally multiplexed with digital serial input 3) spdif1 25 apio spdif1 data input (internally multiplexed with digital serial input 2) tscan 26 ipthdt5v scan control active high (internal pull down) sysclk 27 bpt4mthdt5v n f s output of SAA7715AH iis_out4 28 ops5c data pin of digital serial output 4 iis_out3 29 ops5c data pin of digital serial output 3 iis_out2 30 ops5c data pin of digital serial output 2 iis_out1 31 ops5c data pin of digital serial output 1 iis_ws 32 ops5c word select output belonging to digital serial output 1 to 4 iis_bck 33 ops5c bit clock output belonging to digital serial output 1 to 4 voutl 34 apio analog left output pin. v dda1 35 vddo fsdac positive supply voltage (bond out to 2 pads) voutr 36 apio analog right output pin v ssa1 37 vsso fsdac ground supply voltage (bond out to 2 pads) vrefda 38 apio voltage reference pin of fsdac pom 39 apio power-on mute pin of fsdac powerdown 40 iptht5v standby mode of chip 2003 mar 13 7 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH table 1 brief explanation of used pin types div_clk_in 41 ipthdt5v divide the input frequency on pin clk_in by two dsp_inout5 42 bpts5thdt5v digital input/output ?ag of the dsp-core (f5 of the status register) dsp_inout6 43 bpts5thdt5v digital input/output ?ag of the dsp-core (f6 of the status register) dsp_inout7 44 bpts5thdt5v digital input/output ?ag of the dsp-core (f7 of the status register) pin type explanation apio analog i/o pad cell; actually pin type vddco bpts5thdt5v 43 mhz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; ttl; hysteresis; pull-down; 5 v tolerant bpts5tht5v 43 mhz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; ttl; hysteresis; 5 v tolerant bpt4mthdt5v bidirectional pad; push-pull input; 3-state output; 4 ma output drive; ttl; hysteresis; pull-down; 5 v tolerant iic400kt5v i 2 c-bus pad; 400 khz i 2 c-bus speci?cation; 5 v tolerant ipthdt5v input pad buffer; ttl; hysteresis; pull-down; 5 v tolerant iptht5v input pad buffer; ttl; hysteresis; 5 v tolerant ipthut5v input pad buffer; ttl; hysteresis; pull-up; 5 v tolerant ops5c output pad; push-pull; 5 ns slew rate control; cmos op4mc output pad; push-pull; 4 ma output drive vddco v dd supply to core only vdde v dd supply to peripheral only vddi v dd supply to core only vddo v dd supply to core only vssco v ss supply to core only (vssco does not connect the substrate) vsse v ss supply to peripheral only vssi v ss supply to core and peripheral vssis v ss supply to core only; with substrate connection vsso v ss supply to core only symbol pin pin type description 2003 mar 13 8 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 SAA7715AH mhc319 iis_bck iis_ws iis_out1 iis_out2 iis_out4 sysclk tscan spdif1 spdif2 v dde iis_bck1 iis_ws1 iis_in1 reserved1 iis_in4 iis_in2 reserved3 iis_in3 a0 iis_out3 dsp_inout6 dsp_inout5 div_clk_in powerdown pom vrefda voutr v dda1 voutl dsp_inout7 v ssa1 sda v ssi1 v ssa2 v ddi1 v dda2 dsp_reset shtcb v sse clk_in scl rtcb reserved2 v ssi2 fig.2 pin configuration. 2003 mar 13 9 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 8 functional description 8.1 pll clock division factors for different clock inputs an on-chip pll generates the clock for the dsp. the dsp runs at a selectable frequency of maximum 70 mhz. the clock is generated with the pll that uses the clk_in of the chip to generate the dsp clock. table 2 gives the pll clock division factor and the values of the dsp_turbo and the div_clk_in bits that need to be set via the i 2 c-bus (see table 10). table 2 pll clock division factor per clock input. the above table does not imply that the clock input is restricted to the values given in this table. the clock input is restricted to be within the range of 8.192 to 12.228 mhz. for higher clock frequencies pin div_clk_in should be set to logic 1 performing a divide-by-2 of the clk_in signal and thereby doubling the clk_in frequency range that is allowed (16.384 to 24.576 mhz). 8.2 the word select pll a second on-chip pll generates a selectable multiple of the sample rate frequency supplied on the word select pin iis_ws (= iis_ws1). the clock generated by this so called ws_pll is available for the user at pin sysclk. tables 3 and 4 show the i 2 c-bus settings needed to generate the n f s clock. the memory map of the i 2 c-bus bits is shown in table 10. table 3 word select input range selection table 4 selection of n f s clock at sysclk output clk_in (mhz) pll_div[4:0] n dsp_turbo div_clk_in dsp clock (mhz) 8.192 (32 khz 256) 10h 272 1 0 69.632 9.728 (38 khz 256) 09h 227 1 0 69.008 11.2896 (44.1 khz 256) 03h 198 1 0 69.854 12.288 (48 khz 256) 00h 181 1 0 69.504 16.384 (32 khz 512) 10h 272 1 1 69.632 18.432 (32 khz 576) 0bh 244 1 1 68.544 19.456 (38 khz 512) 09h 227 1 1 69.008 24.576 (96 khz 256) 00h 181 1 1 69.504 sample rate of f s (khz) sel_loop_div[1:0] 32 to 50 01 50 to 96 00 sel2 sel1 sel0 sysclk (n iis_ws1) duty factor 1 0 0 512 50% for 32 to 50 khz input; 66% for 50 to 96 khz input 0 1 1 384 50% 0 1 0 256 50% 0 0 1 192 50% 0 0 0 128 50% 2003 mar 13 10 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 8.3 the filter stream dac (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post-filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. 8.3.1 i nterpolation filter the digital filter interpolates from 1 to 64f s by means of a cascade of a recursive filter and an fir filter. table 5 digital interpolation ?lter characteristics 8.3.2 n oise shaper the 5th-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 8.3.3 f unction of pin pom with pin pom it is possible to switch off the reference current of the dac. the capacitor on pin pom determines the time after which this current has a soft switch-on. so at power-on the current audio signal outputs are always muted. the loading of the external capacitor is done in two stages via two different current sources. the loading starts at a current level that is lower than the current loading after the voltage on pin pom has passed a particular level. this results in an almost db-linear behaviour. this prevents plop effects during power on/off. 8.3.4 p ower off plop suppression to avoid plops in a power amplifier, the supply voltage of the analog part of the dac and the rest of the chip can be fed from a separate supply of 3.3 v. a capacitor connected to this supply enables to provide power to the analog part at the moment the digital voltage is switching off fast. in this event the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 8.3.5 p in vrefda for internal reference with two internal resistors half the supply voltage v dda1 is obtained and used as an internal reference. this reference voltage is used as dc voltage for the output operational amplifiers and as reference for the dac. in order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground, preferably close to the analog pin v ssa1 . 8.3.6 s upply of the analog outputs the entire analog circuitry of the dacs and the opamps are supplied by 2 supply pins, v dda1 and v ssa1 . the v dda1 must have sufficient decoupling to prevent thd degradation and to ensure a good power supply rejection ratio (psrr). the digital part of the dac is fully supplied from the chip core supply. 8.4 external control pins the flags dsp_inout5 to dsp_inout7 are available as external pins. the flags can be used by the dsp depending on the downloaded software. item conditions value (db) pass band ripple 0 to 0.45f s 0.03 stop band >0.55f s - 50 dynamic range 0 to 0.45f s 116.5 gain dc - 3.5 2003 mar 13 11 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 8.5 digital serial inputs/outputs and spdif inputs 8.5.1 d igital serial inputs / outputs for communication with external digital sources a digital serial bus is implemented. it is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. for external digital sources the SAA7715AH acts as a slave, so the external source is master and supplies the clock. for the i 2 s-bus format itself see the official specification from philips. the digital serial input is capable of handling philips i 2 s-bus and lsb-justified formats of 16, 18, 20 and 24 bits word sizes. the sampling frequency can be 32 up to 96 khz. see 9.8 i 2 c-bus memory map definition for the bits that must be programmed, for selection of the desired serial format. see fig.3 for the general waveforms of the possible formats. when the applied word length exceeds 24 bits, the lsbs are skipped. the digital serial input/output circuitry is limited in handling the number of bck pulses per ws period. the maximum allowed number of bit clocks per ws period is 256. also the number of bit clocks during ws low and high must be equal (50% ws duty factor) only for the lsb-justified formats. there are two modes in which the digital inputs can be used (the mode is selectable via an i 2 c-bus bit): use up to 4 digital serial inputs (8ch) with common ws and bck signal (8ch in and 8ch out + 2ch fsdac output) use one of the 2 spdif inputs as source instead of the use of the digital serial inputs (2ch in and 8ch out + one 2ch fsdac output). 8.5.2 spdif inputs two separate spdif receivers are available, one shared with digital serial input 2 (spdif1) and one with the digital serial input 3 (spdif2). the sample frequency at which the spdif inputs can be used must be in the range of 32 to 96 khz. there are few control signals available from the spdif input stage. these are connected to flags of the dsp: a lock signal indicating if the spdif input 1 or 2 is in lock the pcm_audio/non-pcm_audio bit indicating if an audio or data stream is detected on spdif input 1 or 2. the fsdac output will not be muted in the event of non-audio pcm stream. this status bit can be read via the i 2 c-bus, the microprocessor controller can decide to put the dac into mute (via pin pom). handling of channel status bits: the first 40 (of 192) channel status bits of the selected spdif source (0ffbh, bit 20), will come available in the i 2 c-bus registers 0ff2h to 0ff5h. two registers 0ff2h to 0ff3h contain the information for the right channel, the other two (0ff4h to 0ff5h) contain the information for the left channel. the information can be read via i 2 c-bus or by the dsp program. the design fulfils the digital audio interface specification iec 60958-1 ed2, part 1, general part iec 60958-3 ed2, part 3, consumer applications . 2003 mar 13 12 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgr751 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left input format i 2 s-bus ws bck data right 3 > = 8 msb b2 fig.3 all serial data input/output formats. 2003 mar 13 13 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 8.6 i 2 c-bus interface (pins scl and sda) the i 2 c-bus format is described in the i 2 c-bus and how to use it , order no. 9398 393 40011. for the external control of the SAA7715AH a fast i 2 c-bus is implemented. this is a 400 khz bus which is downward compatible with the standard 100 khz bus. there are two different types of control instructions: loading of the program ram (pram) with the required dsp program C programming the coefficient ram (yram) C instructions to control the dsp program. selection of the digital serial input/output format to be used, the dsp clock speed. the detailed description of the i 2 c-bus and the description of the different bits in the memory map is given in chapter 9. 8.7 reset the reset (pin dsp_reset) is active low and needs an external 22 k w pull-up resistor. between this pin and the v ssi ground a capacitor of 1 m f should be connected to allow a proper switch-on of the supply voltage. the capacitor value is such that the chip is in reset as long as the power supply is not stabilized. a more or less fixed relationship between the dsp reset and the pom time constant is obligatory. the voltage on pin pom determines the current flowing in the dacs. the reset sets all i 2 c-bus bits to their default value and it restarts the dsp program. 8.8 power-down mode the power-down mode switches off all activity on the chip. the power-down mode can be switched on and off using pin powerdown. this pin needs to be connected to ground if not used. the following applies for the power-down mode: power-down mode may only be switched on when there is no i 2 c-bus activity to or from the SAA7715AH power-down mode may not be switched on before the complete chip has been reset (dsp_reset active low) the clock signal on pin clk_in should be running during power-down mode it is advised to set pin pom to logic 0 before switching on the power-down mode and set it back to logic 1 after the chip actually returns from power-down mode as shown in fig.4 all on-chip registers and memories will keep their values during power-down mode digital serial outputs are not muted, the last value is kept on the output the SAA7715AH will not lock-up the i 2 c-bus during power-down mode (sda line). figure 4 shows the time the chip actually is in power-down mode after switching on/off pin powerdown. handbook, full pagewidth mgt828 t a t b powerdown device actually in power-down mode pom clk_in fig.4 power-down mode. t a =4 (256/clk_in); 8.192 mhz < clk_in < 12.288 mhz. t a =4 (512/clk_in); 16.384 mhz < clk_in < 24.576 mhz. t b = 128 (256/clk_in); 8.192 mhz < clk_in < 12.288 mhz. t b = 128 (512/clk_in); 16.384 mhz < clk_in < 24.576 mhz. 2003 mar 13 14 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 8.9 power supply connection and emc the digital part of the chip has in total 4 positive supply line connections and 5 ground connections. to minimize radiation the chip should be put on a double layer printed-circuit board with on one side a large ground plane. the ground supply lines should have a short connection to this ground plane. a coil/capacitor network in the positive supply line of the peripheral power supply line can be used as high frequency filter. the core supply lines (v ddi ) have an on-chip decoupling capacitance, for emc reasons an external decoupling capacitance must not be used on this pin. a series resistor plus capacitance is required for proper operation on pin v dda2 , see fig.9. 8.10 test mode connections (pins tscan, rtcb and shtcb) pins tscan, rtcb and shtcb are used to put the chip in test mode and to test the internal connections. each pin has an internal pull-down resistor to ground. in the application these pins can be left open or connected to ground. 9i 2 c-bus protocol 9.1 addressing before any data is transmitted on the i 2 c-bus, the device that should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. 9.2 slave address (pin a0) the SAA7715AH acts as a slave receiver or a slave transmitter. therefore the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the slave address is shown in table 6. table 6 slave address the sub-address bit a0 corresponds to the hardware address pin a0 which allows the device to have 2 different addresses. the a0 input is also used in test mode as serial input of the test control block. 9.3 write cycles the i 2 c-bus configuration for a write cycle is shown in fig.5. the write cycle is used to write the bytes to the dsp for manipulating the data and coefficients. more details can be found in the i 2 c-bus memory map, see table 8. the data length is 2, 3 or 4 bytes depending on the accessed memory. if the y-memory is addressed the data length is 2 bytes, in the event of the x-memory the length is 3 bytes. the slave receiver detects the address and adjusts the number of bytes accordingly. for this ram-based product the internal p-memory (pram) can be accessed via the i 2 c-bus interface. the transmitted data stream should be 4 bytes. 9.4 read cycles the i 2 c-bus configuration for a read cycle is shown in fig.6. the read cycle is used to read the data values from xram, yram or pram. the master starts with a start condition s, the SAA7715AH address 0011110 and a logic 0 (write) for the read/write bit. this is followed by an acknowledge of the SAA7715AH. then the master writes the high memory address (addr h) and low memory address (addr l) where the reading of the memory content of the SAA7715AH must start. the SAA7715AH acknowledges these addresses both. the master generates a repeated start (sr) and again the SAA7715AH address 0011110 but this time followed by a logic 1 (read) of the read/write bit. from this moment on the SAA7715AH will send the memory content in groups of 3 (x/y-memory or registers) or 4 (p-memory) bytes to the i 2 c-bus each time acknowledged by the master. the master stops this cycle by generating a negative acknowledge, then the SAA7715AH frees the i 2 c-bus and the master can generate a stop condition. the data is transferred from the dsp register to the i 2 c-bus register at execution of the mpi instruction in the dsp program. therefore at least once every dsp routine an mpi instruction should be added. msb lsb 0 0 1 1 1 1 a0 r/ w 2003 mar 13 15 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 0111100 a c k a c k a c k a c k a c k address s 0 addr h addr l data 1 data ... r/w mgu331 auto increment if repeated n-groups of 2, 3 or 4 bytes p a c k data 4 fig.5 master transmitter writes to the SAA7715AH registers. s = start condition. p = stop condition. ack = acknowledge from SAA7715AH. addr h and addr l = address dsp register. data 1 to data 4 = 2, 3 or 4 bytes data word. 0111100 a c k a c k a c k a c k a c k address s 0 011 1 110 s r 0 addr h addr l data 1 r/w mgu330 auto increment if repeated n-groups of 2, 3 or 4 bytes r a c k p n a a c k data ... data 4 r/w fig.6 master transmitter reads from the SAA7715AH registers. s = start condition. sr = repeated start condition. p = stop condition. ack = acknowledge from SAA7715AH (sda low). r = repeat n-times the 2, 3 or 4 bytes data group. na = negative acknowledge master (sda high). addr h and addr l = address dsp register. data 1 to data 4 = 2, 3 or 4 bytes data word. 2003 mar 13 16 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 9.5 program ram the SAA7715AH has a 1.5 kbyte pram to store the dsp instruction code into. also a 2 kbyte prom is on-chip available and can be accessed (memory mapped) without the need of selecting the prom or pram. the dsp instruction code can be downloaded into the pram via the i 2 c-bus. the write and read cycle are shown in figs 5 and 6 respectively. the dsp has an instruction word width of 32 bits which means that this space should be accessed with 4 bytes in consecutive order and does have the auto-increment function. 9.6 data word alignment it is possible to transfer data via the i 2 c-bus to a destination where it can have different data word length. those destinations with data word are shown in table 7. table 7 data word alignment source destination data word bytes (number) i 2 c-bus dsp-pram mbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbl 4 i 2 c-bus dsp and general control mbbb bbbb bbbb bbbb bbbb bbbl 3 i 2 c-bus i 2 c-bus registers mbbb bbbb bbbb bbbb bbbb bbbl 3 i 2 c-bus dsp-xram mbbb bbbb bbbb bbbb bbbb bbbl 3 i 2 c-bus dsp-yram xxxx mbbb bbbb bbbl 2 2003 mar 13 17 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 9.7 i 2 c-bus memory map speci?cation the i 2 c-bus memory map contains all defined i 2 c-bus bits. the map is split up in two different sections: the hardware memory registers and the ram definitions. in table 8 the preliminary memory map is depicted. the hardware registers are memory map on the xram of dsp. table 9 shows the detailed memory map of those locations. all locations are acknowledged by the SAA7715AH even if the user tries to write to a reserved space. the data in these sections will be lost. reading from these locations will result in undefined data words. table 8 i 2 c-bus memory map table 9 i 2 c-bus memory map overview address function size 8000h to 87ffh dsp to prom (not readable via i 2 c-bus) 2k 32 bits 602fh dsp and general control 1 24 bits 2000h to 25ffh dsp to pram 1.5k 32 bits 1000h to 15ffh dsp to yram 1.5k 12 bits 0ff2h to 0ff5h, 0ffbh i 2 c-bus register 5 24 bits 0000h to 0b7fh dsp to xram 2.875k 24 bits address description hardware registers 0ffbh selector register 1 0ff5h spdif in channel status register 1 left 0ff4h spdif in channel status register 2 left 0ff3h spdif in channel status register 1 right 0ff2h spdif in channel status register 2 right dsp control 602fh dsp and general control register 2003 mar 13 18 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 9.8 i 2 c-bus memory map de?nition table 10 dsp and general control register (602fh) table 11 spdif in channel status register 2 right (0ff2h) table 12 spdif in channel status register 1 right (0ff3h) name size (bits) description default bit position 1 reserved 0 0 pll_div[4:0] 5 pll clock division factor according to table 2 00011 5 to 1 dsp_turbo 1 pll output frequency 1 6 1: double 0: no doubling 1 reserved 1 7 pc_reset_dsp 1 program counter reset dsp 0 8 1: reset on 0: reset off 2 reserved 00 10 to 9 sel[2:0] 3 selection of n f s clock at sysclk output according to ta b l e 4 010 13 to 11 sel_loop_div[1:0] 2 word select input range selection for ws_pll according to table 3 01 15 to 14 2 reserved 00 17 to 16 sel_fsdac_clk 2 clock source for fsdac 00 19 to 18 00: ws_pll if no signal to pin clk_in 01: 512f s to pin clk_in 11: 256f s to pin clk_in dis_sysclk 1 output on pin sysclk 0 20 1: disable 0: enable 256f s _n*fs 1 signal on pin sysclk 0 21 1: fixed 256f s clock 0: n f s clock; determined by bits 13 to 11 2 reserved 00 23 to 22 name size (bits) description default bit position ch_stat_in right lsb 20 channel status spdif in right lsb bits 19 to 0 00000h 19 to 0 name size (bits) description default bit position ch_stat_in right msb 20 channel status spdif in right msb bits 39 to 20 00000h 19 to 0 2003 mar 13 19 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH table 13 spdif in channel status register 2 left (0ff4h) table 14 spdif in channel status register 1 left (0ff5h) table 15 selector register 1 (0ffbh) name size (bits) description default bit position ch_stat_in left lsb 20 channel status spdif in2 left lsb bits 19 to 0 00000h 19 to 0 name size (bits) description default bit position ch_stat_in left msb 20 channel status spdif in2 left msb bits 39 to 20 00000h 19 to 0 name size (bits) description default bit position format_in1 3 digital serial inputs 1 and 4 data format according to ta b l e 1 7 011 2 to 0 format_in2 3 digital serial input 2 data format according to table 17 011 5 to 3 format_in3 3 digital serial input 3 data format according to table 17 011 8 to 6 format_out 3 digital serial outputs 1 to 4 data format according to ta b l e 1 8 000 11 to 9 en_output 1 enable or disable digital serial outputs 1 12 1: enable 0: disable 1 reserved 0 13 master_source 4 source selection 0000 17 to 14 0000: digital serial input 1 0101: digital serial input 2 or spdif 1 (see bit 18) 1010: digital serial input 3 or spdif 2 (see bit 19) all other values are reserved spdif_sel1 1 spdif1 or digital serial input 2 0 18 1: spdif1 0: digital serial input 2 spdif_sel2 1 spdif2 or digital serial input 3 0 19 1: spdif2 0: digital serial input 3 sel_spdi?n_chstat 1 select channel status information taken from spdif1 or spdif2 020 1: from input spdif2 0: from input spdif1 3 reserved 000 23 to 21 2003 mar 13 20 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH table 16 default settings of i 2 c-bus registers after power-up and reset 9.9 table de?nitions table 17 digital serial format for inputs 1 to 4 table 18 digital serial formats for outputs 1 to 4 10 software in rom description the function of this chip is related to the prom code (rom code dependent). i 2 c-bus address default value 602fh 0050c6h 0ffbh 0010dbh 0ff5h 000000h 0ff4h 000000h 0ff3h 000000h 0ff2h 000000h format_in1, 2 and 3 input bit 2 bit 1 bit 0 0 1 1 standard i 2 s-bus 1 0 0 lsb-justi?ed, 16 bits 1 0 1 lsb-justi?ed, 18 bits 1 1 0 lsb-justi?ed, 20 bits 1 1 1 lsb-justi?ed, 24 bits format_out output bit 2 bit 1 bit 0 0 0 0 standard i 2 s-bus 1 0 0 lsb-justi?ed, 16 bits 1 0 1 lsb-justi?ed, 18 bits 1 1 0 lsb-justi?ed, 20 bits 1 1 1 lsb-justi?ed, 24 bits 2003 mar 13 21 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 11 limiting values in accordance with the absolute maximum ratings system (iec 60134). notes 1. machine model (r = 0 w ; c = 100 pf; l = 2.5 m h). 2. human body model (r = 1500 w ; c = 100 pf). 12 thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +3.6 v v i input voltage - 0.5 +5.5 v i ik input clamping diode current v i < - 0.5 v or v i >v dd + 0.5 v - 10 ma i ok output clamping diode current v o < - 0.5 v or v o >v dd + 0.5 v - 20 ma i o(sink/source) output source or sink current - 0.5v 2003 mar 13 23 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH v ol low-level output voltage standard output; i o =4ma -- 0.4 v 5 ns slew rate output; i o =4ma -- 0.4 v 10 ns slew rate output; i o =2ma -- 0.4 v 20 ns slew rate output; i o =1ma -- 0.4 v i 2 c-bus output; i o =4ma -- 0.4 v i lo output leakage current 3-state outputs v o = 0 v or v dd -- 5 m a r pd internal pull-down resistor to v ss 24 50 140 k w r pu internal pull-up resistor to v dd 30 50 100 k w c i input capacitance -- 3.5 pf t i(r) ,t i(f) input rise and fall times v dd = 3.45 v - 6 200 ns t o(t) output transition time standard output; c l =30pf - 3.5 - ns 5 ns slew rate output; c l =30pf - 5 - ns 10 ns slew rate output; c l =30pf - 10 - ns 20 ns slew rate output; c l =30pf - 20 - ns i 2 c-bus output; c l = 400 pf 60 - 300 ns ac characteristics spdif1 and spdif2 inputs; t amb =25 c; v dda2 = 3.3 v; unless otherwise speci?ed v i(p-p) ac input level (peak-to-peak level) 0.2 0.5 3.3 v r i input impedance at 1 khz - 6 - k w v hys hysteresis of input voltage - 40 - mv analog dac outputs; v dda1 = 3.3 v; f s = 44.1 khz; t amb =25 c; r l =5k w ; all voltages referenced to ground; unless otherwise speci?ed dc characteristics r o(dac) dac output resistance - 0.13 3.0 w i o(max) maximum output current (thd + n)/s < 0.1% r l =5k w - 0.22 - ma r l load resistance 3 -- k w c l load capacitance -- 200 pf r o(vrefda) vrefda output resistance - 28 - k w ac characteristics v o(rms) output voltage (rms value) - 1000 - mv d v o unbalance between channels - 0.1 - db symbol parameter conditions min. typ. max. unit 2003 mar 13 24 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db -- 85 - db(a) at - 60 db -- 37 - db(a) s/n signal-to-noise ratio code = 0 - 100 - db(a) a cs channel separation - 80 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) =1% - 50 - db symbol parameter conditions min. typ. max. unit 2003 mar 13 25 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 14 i 2 s-bus timing handbook, full pagewidth ws bck data in right lsb msb left t su(ws) t h(ws) t su(d) t h(d) t bck(h) t d(d) t bck(l) t cy t r t f mgm129 data out lsb msb fig.7 timing of the digital serial audio data inputs and outputs. table 19 timing of the digital serial audio data inputs and outputs (see fig.7) symbol parameter conditions min. typ. max. unit t cy bit clock cycle time 162 -- ns t r rise time t cy =50ns -- 0.15t cy ns t f fall time t cy =50ns -- 0.15t cy ns t bck(h) bit clock high time t cy = 50 ns 0.35t cy -- ns t bck(l) bit clock low time t cy = 50 ns 0.35t cy -- ns t su(d) data set-up time t cy = 50 ns 0.2t cy -- ns t h(d) data hold time t cy = 50 ns 0.2t cy -- ns t d(d) data delay time t cy =50ns -- 0.15t cy ns t su(ws) word select set-up time t cy = 50 ns 0.2t cy -- ns t h(ws) word select hold time t cy = 50 ns 0.2t cy -- ns 2003 mar 13 26 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 15 i 2 c-bus timing handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.8 timing of the i 2 c-bus. table 20 timing of the i 2 c-bus (see fig.8) symbol parameter conditions standard mode i 2 c-bus fast mode i 2 c-bus unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 -m s t hd;sta hold time (repeated) start condition; after this period, the ?rst clock pulse is generated 4.0 - 0.6 -m s t low scl low period 4.7 - 1.3 -m s t high scl high period 4.0 - 0.6 -m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 -m s t hd;dat data hold time 0 - 0 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals c b in pf - 1000 20 + 0.1c b 300 ns t f fall time of both sda and scl signals c b in pf - 300 20 + 0.1c b 300 ns t su;sto set-up time for stop condition 4.0 - 0.6 -m s c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes to be suppressed by input ?lter not applicable 0 50 ns 2003 mar 13 27 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 16 application diagram handbook, full pagewidth mhc321 4.7 k w 4.7 k w 22 k w 100 w 100 w 10 k w 10 k w 22 k w 47 m f 47 m f 47 m f 1 m f (1) 100 nf 100 nf 100 nf 100 nf 4.7 m f + 5 v + 5 v + 3.3 v + 3.3 v SAA7715AH tcb pram prom dsp core stereo dac n f s clock i 2 c-bus ws_pll i 2 c-bus 2 pll 1 iis_bck1 2 24 25 iis_ws1 3 iis_in1 5 iis_in4 iis_out1 31 iis_out2 30 iis_out3 29 iis_out4 28 voutl 34 voutr 36 iis_bck 33 iis_ws 32 pom 39 vrefda 38 digital inputs digital outputs 9 22 41 iis_in3 clk_in div_clk_in 6 dsp clock dsp flags microcontroller microcontroller microcontroller right output left output iis_in2 s xram yram l1 l2 44 dsp_inout7 43 dsp_inout6 42 dsp_inout5 20 shtcb 19 rtcb v ssi2 26 tscan 27 10 v ssi1 14 v sse 21 v ssa2 15 v ddi1 16 v dde 23 v dda2 17 v dda1 spdif2 spdif1 35 v ssa1 37 sysclk 18 dsp_reset 13 sda 12 scl 11 a0 40 powerdown 10 w 10 w 75 w 47 m f 47 m f 47 m f 100 nf spdif input signals 100 nf 100 pf 75 w 100 pf 4 reserved1 7 reserved2 8 reserved3 fig.9 application diagram. (1) omit this capacitor when a microcontroller is used. 2003 mar 13 28 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1 2003 mar 13 29 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2003 mar 13 30 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable 2003 mar 13 31 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 19 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 mar 13 32 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH 22 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2003 mar 13 33 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH notes 2003 mar 13 34 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH notes 2003 mar 13 35 philips semiconductors preliminary speci?cation digital signal processor SAA7715AH notes ? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/01/pp 36 date of release: 2003 mar 13 document order number: 9397 750 10206 |
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